1. Technical Field
The present invention is related to a memory semiconductor device, more particularly, to a multi-level memory device and method of operating the same.
2. Description of Related Art
A phase-change layer has a property of variable electrical resistance depending on its crystalline state, and it may be used to store data in a multi-level memory device. The electrical resistance of the phase-change layer is low in a crystalline state (i.e. a set-state), and high in an amorphous state (i.e. a reset-state). Therefore, the crystalline state of the phase-change layer corresponding to the stored data may be verified by measuring the electrical resistance of the phase-change layer.
The crystalline state of the phase-change layer may be controlled by time and temperature.
FIG. 1 is a graph illustrating variation of crystalline state of the phase-change layer according to time and temperature. In the graph, the x-axis indicates time (T), and the y-axis indicates temperature (TMP).
Referring to FIG. 1, when the phase-change layer is heated at a temperature higher than the melting temperature (Tm) for a first duration (T1), then cooled, the phase-change layer becomes an amorphous state {circle around (1)}. Also, when the phase-change layer is heated at a temperature lower than the melting temperature (Tm) and higher than the crystallization temperature (Tc) for a second duration (T2), then cooled, the phase-change layer becomes a crystalline state {circle around (2)}. Here, the second duration (T2) is a longer term than the first duration T1.
Recently, in order to meet the increased demand in memory capacity in memory semiconductor devices, a multi-level cell, which stores a plurality of data in a single memory cell, has been introduced. In order to realize such a multi-level cell in a multi-level memory device, a method of controlling volume of the crystallized area in the phase-change layer is introduced. As described above, as each phase-change layer has different resistance according to its crystalline state, the total resistance level of the phase-change memory cell of this method is determined by the volume rate of the amorphous or crystalline region of the phase-change layer. Therefore, in order to realize the multi-level cell, discrete control of the volume of the region where the crystalline state changes is required. However, as the crystallization of the phase-change layer depends on the temperature, which is a parameter that is difficult to control spatially, the discrete control of the volume of the phase-changeable region is difficult to achieve.
Furthermore, as the resistance level of the phase-change memory cell according to this method is dominantly determined by the resistance level of the amorphous region, there is another problem that it is difficult to realize the multi-level cell. In detail, FIG. 2 illustrates the relation between the volume of the phase-changeable region and the resistance level of the phase-change memory cell. For clarity of description, the phase-change layer will be assumed to include three different phase-changeable regions P1, P2, and P3.
Referring to FIG. 2, since the phase-changeable regions P1, P2, and P3 are connected in series, the total resistance level (R) of the phase-change layer is equal to a sum of R1, R2, and R3, which denote the resistance of the phase-changeable regions P1, P2, and P3, respectively, as, follows:R=R1+R2+R3.   [Equation 1]
To show an example of a numerical analysis, the resistance of each phase-changeable region will be assumed to be 1 kΩ in a set-state (i.e. crystalline state), and 100 kΩ in a reset state (i.e. amorphous state).
TABLE 1State (Resistance)R1Set (1 kΩ)Reset (100 kΩ)Reset (100 kΩ)Reset (100 kΩ)R2Set (1 kΩ)Set (1 kΩ)Reset (100 kΩ)Reset (100 kΩ)R3Set (1 kΩ)Set (1 kΩ)Set (1 kΩ)Reset (100 kΩ)R3 kΩ (~0 kΩ)102 kΩ201 kΩ300 kΩ(~100 kΩ)(~200 kΩ)Data00011011
As shown in the above Table 1, the resistance level R of the total phase-change layer may have four different data states (00, 01, 10, 11) according to the crystalline states of the respective phase-changeable regions P1, P2, and P3, and the data state depends on the number of phase-changeable regions in the reset state.
However, according recent research, as shown in FIG. 3, the resistance level in the reset state varies over time (D. Jelmini et. al., IEEE Transactions on Electron Device, 2007, vol. 54, 308-315). As shown in FIG. 4, the drifts of such resistance lead to a change of the resistance level of the phase-change memory cells, and moreover, the resistance level window, required in order to distinguish the data states, may disappear. Particularly, in a structure where the phase-changeable regions are connected in series, since the time-depending drift of resistance is also given by the Equation 1, the change in the resistance of the data states increase in proportion to the number of the phase-changeable regions, which are in the reset state.